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SM5950AM Asynchronous Sample Rate Converter
OVERVIEW
The SM5950AM is a digital audio signal asynchronous sample rate converter LSI. It supports 16/20/24-bit word-length input/output interface data. It also features a built-in digital deemphasis filter and direct mute functions.
FEATURES
Functions
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PINOUT
(Top view)
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L/R 2-channel (stereo) processing Input sample rate range: 20kHz to 100kHz Output sample rate range: 30kHz to 50kHz Operating sample rate conversion ratio (fso/fsi)*1 : 0.45 to 2.205 selectable *1: fsi = input sample rate fso = output sample rate Asynchronous input and output clock timing System clock input * Input system clock: 1fsi (LRCI) * Output system clock: 512fso (SCKO input) Deemphasis filter function * IIR-type filter * fsi = 44.1kHz, 48kHz, 32kHz compatible Direct mute function Through mode operation * Direct connection from input to output Output data clocks (LRCO, BCKO) * Slave mode: external inputs * Master mode: derived from the output system clock (SCKO) Computation round-off processing * Normal round-off 5V tolerant input pins for direct connection to 5V operation devices 3.3V single supply Package: 24-pin SSOP
LRCI BCKI DI TMOD0 RSTN VDD IISI IMOD0 IMOD1 DEEM FS0 FS1
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
LRCO BCKO DOUT SLAVE SCKO VSS IISO OMOD0 OMOD1 TMOD1 THROU DMUTE
PACKAGE DIMENSIONS
(Unit: mm) Weight: 0.23g
10.20 0.30 10.05 0.20
+ 0.15 - 0.10 0.05
5.40 0.20
Device SM5950AM
Package 24-pin SSOP
1.80
0 to 10
0.10 0.10
0.36 0.10 0.10
0.12
M
Note: Dimensions without tolerance are reference values.
NIPPON PRECISION CIRCUITS INC.--1
+ 0.20 1.90 - 0.10
0.8
0.50 0.20
ORDERING INFORMATION
7.80 0.30
SM5950AM
FEATURES
Interfaces
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Converter Performance
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Input data format * 2s-complement, MSB-first, L/R alternating serial data * IIS/non-IIS formats
Format IMOD0 L H L H H or L IMOD1 L L H H H or L IISI L L L L H
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16-bit MSB-first right-justified 20-bit MSB-first right-justified 24-bit MSB-first right-justified MSB-first left-justified (leading 16 bits valid data) IIS (leading 16 bits valid data)
L = Low input level, H = high input level
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Output data format * 2s-complement, MSB-first, L/R alternating serial data * Bit clock continuous (64fso)
Format OMOD0 L H L H H or L OMOD1 L L H H H or L IISO L L L L H
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16-bit MSB-first right-justified 20-bit MSB-first right-justified 24-bit MSB-first right-justified MSB-first left-justified (16-bit output) IIS (16-bit output)
L = Low input level, H = high input level
Internal data word length: 20 bits Deemphasis filter characteristics (IIR filter) * 0.03dB gain deviation from ideal filter characteristic Anti-aliasing LPF characteristics (6 types of FIR filter) * Output/input sample rate conversion ratio automatic filter select (6 FIR filters) 1. Up converter LPF 1.0 to 2.205 times 2. Down converter LPF I about 0.92 times: 48.0kHz to 44.1kHz 3. Down converter LPF II about 0.73 times: 44.1kHz to 32.0kHz 4. Down converter LPF III about 0.67 times: 48.0kHz to 32.0kHz 5. Down converter LPF IV about 0.50 times: 96.0kHz to 48.0kHz 6. Down converter LPF V about 0.45 times: 96.0kHz to 44.1kHz - Passband ripple: 0.0001dB - Stopband attenuation: > 98dB Converter insertion quantization noise level * Internal calculation (quantization) noise : - 96dB * Output round-off noise: - 16-bit output mode : - 98dB - 20-bit output mode : - 122dB - 24-bit output mode : - 146dB * Output S/N ratio (theoretical values)
Output signal word length 16 bits 20 bits S/N ratio 16-bit input 20-bit input 24-bit input - 92.5dB - 93.9dB - 93.9dB - 94.0dB - 96.2dB - 96.2dB - 94.0dB - 96.2dB - 96.2dB
Structure
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Silicon-gate CMOS process
Applications
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Digital audio equipment-interface sample rate conversion * AV amplifier, CD-R/RW, DAT, MD, DVC Recording/editing equipment sample rate conversion
24 bits
NIPPON PRECISION CIRCUITS INC.--2
SM5950AM
BLOCK DIAGRAM
LRCI
BCKI
DI
IMOD0 Input data interface IMOD1 IISI
SCKO RSTN
Sequencer block
Arithmetic operation block Interpolation filter operation
Interpolation operation
Output data operation
DEEM Deemphasis filter operation FS0 FS1
Conversion rate detector
Filter type selector Output operation Output timing operation
IISO OMOD0 OMOD1 THROU SLAVE DMUTE Though, mute, and slave mode control Output data interface
LRCO BCKO DOUT
NIPPON PRECISION CIRCUITS INC.--3
SM5950AM
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name LRCI BCKI DI TMOD0 RSTN VDD IISI IMOD0 IMOD1 DEEM FS0 FS1 DMUTE THROU TMOD1 OMOD1 OMOD0 IISO VSS SCKO SLAVE DOUT BCKO LRCO I/O I I I I I - I I I I I I I I I I I I - I I O I/O I/O Sample rate clock input (fsi) Bit clock input (32fsi to 64fsi) Data input IC test mode select pin (must be LOW for normal operation) Reset pin VDD supply (3.3V) IIS input select pin Input format select pin 0 Input format select pin 1 Deemphasis select pin Deemphasis frequency select pin 0 Deemphasis frequency select pin 1 Direct mute select pin Through mode select pin IC test mode select pin (must be LOW for normal operation) Output format select pin 1 Output format select pin 0 IIS output select pin GND connection (0V) Output system clock input (512fso) Slave select pin Data output Bit clock input/output (64fso) Sample rate clock input/output (fso) Description HIGH - - - Test - - - - - ON - - ON Through Test - - - - - Slave - - - LOW - - - Normal Reset - - - - OFF - - OFF SRC Normal - - - - - Master - - -
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SM5950AM
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0V, VDD pin voltage = VDD
Parameter Supply voltage range Input voltage range Output voltage range Storage temperature range Power dissipation Symbol VDD VI VO Tstg PD Rating - 0.3 to 4.6 - 0.3 to 5.5 - 0.3 to VDD + 0.3 - 55 to 125 400 Unit V V V C mW
Note: Ratings also apply at supply switch ON and OFF.
Recommended Operating Conditions
VSS = 0V, VDD pin voltage = VDD
Rating Parameter Supply voltage Operating temperature Symbol min VDD Topr 3.0 - 40 typ 3.3 25 max 3.6 85 V C Unit
DC Electrical Characteristics
VSS = 0V, VDD = 3.0 to 3.6V, Ta = -40 to 85C
Rating Parameter Current consumption HIGH-level input voltage (*1) (*3) LOW-level input voltage HIGH-level output voltage (*2) (*3) LOW-level output voltage Input leakage current (*1) (*3) Pin VDD Symbol IDD VIH VIL VOH VOL ILH ILL IOH = -2.0mA IOL = 2.0mA VIN = VDD VIN = 0V (*A) Condition min - 2.0 0 2.4 0 - 1.0 - 1.0 typ 22.0 - - - - - - max 30.0 5.5 0.7 VDD 0.4 1.0 1.0 mA V V V V A A Unit
(*A) All output pins with no load, System Clock frequency: FSCKO = 24.576MHz, Input word clock frequency: FLRCI = 48kHz, Supply voltage: VDD = 3.3V
Pin type
Note (*1) (*2) (*3) Type Inputs Output Inputs/Outputs Names LRCI, BCKI, DI, TMOD0, RSTN, IISI, IMOD0, IMOD1, DEEM, FS0, FS1, DMUTE, THROU, TMOD1, OMOD1, OMOD0, IISO, SCKO, SLAVE DOUT BCKO, LRCO
Note: All inputs and input/output pins are 5V compatible. Consequently, input voltages up to 5.5V can be connected. However, while input/output pins in input mode can have input voltage up to 5.5V, input/output pins in output mode have output voltages that do not rise above VDD level. Plus, in output mode, it is prohibited to use external pull-up to raise the voltage above VDD.
NIPPON PRECISION CIRCUITS INC.--5
SM5950AM
AC Electrical Characteristics
Output system clock (SCKO input)
Rating Parameter Clock pulse cycle time Clock pulsewidth (HIGH level) Clock pulsewidth (LOW level) Clock pulse duty Symbol tCY tCWH tCWL Condition min 39.0 15.6 15.6 40 typ - - - - max 65.1 39.1 39.1 60 ns ns ns % Unit
VIH SCKO 0.5VDD V IL t CWH t CY t CWL
Reset input (RSTN)
Rating Parameter RSTN pulsewidth Symbol tRST Condition min 39 typ - max - ns Unit
VIH RSTN 0.5VDD V IL t RST
NIPPON PRECISION CIRCUITS INC.--6
SM5950AM Serial inputs (LRCI, BCKI, DI)
Rating Parameter LRCI cycle time BCKI pulse cycle time BCKI pulsewidth (HIGH level) BCKI pulsewidth (LOW level) DI setup time DI hold time Last BCKI rising edge to LRCI edge LRCI edge to first BCKI rising edge Symbol tLICY tBICY tBICWH tBICWL tDIS tDIH tBLI tLBI Condition min 10 156.25 60 60 30 30 30 30 typ - - - - - - - - max 50 1562.5 - - - - - - s ns ns ns ns ns ns ns Unit
VIH LRCI 0.5VDD V IL t BLI t LBI VIH BCKI 0.5VDD V IL t BICWH t BICY VIH DI 0.5VDD V IL t DIS t DIH t BICWL
NIPPON PRECISION CIRCUITS INC.--7
SM5950AM Serial outputs (SLAVE = HIGH, LRCO, BCKO inputs, DOUT output)
Rating Parameter LRCO cycle time BCKO pulse cycle time BCKO pulsewidth (HIGH level) BCKO pulsewidth (LOW level) Last BCKO rising edge to LRCO edge LRCO edge to first BCKO rising edge DOUT output delay Symbol tLOCY tBOCY tBOCWH tBOCWL tBLO tLBO tDODL CL = 15pF Condition min 20 312.5 125 125 30 30 - typ - - - - - - - max 33.34 1041.7 - - - - 30 s ns ns ns ns ns ns Unit
VIH LRCO 0.5VDD V IL t BLO t LBO VIH BCKO 0.5VDD V IL t BOCWH t BOCY VOH DOUT 0.5VDD V OL t DODL t BOCWL
NIPPON PRECISION CIRCUITS INC.--8
SM5950AM Serial outputs (SLAVE = LOW, LRCO, BCKO, DOUT outputs)
Rating Parameter LRCO cycle time LRCO pulsewidth (HIGH level) LRCO pulsewidth (LOW level) BCKO pulse cycle time BCKO pulsewidth (HIGH level) BCKO pulsewidth (LOW level) BCKO output delay LRCO output delay DOUT output delay Symbol tLOCY tLOCWH tLOCWL tBOCY tBOCWH tBOCWL tBODL tLODL tDODL CL = 15pF CL = 15pF CL = 15pF Condition min - - - - - - - - - typ 512 256 256 8 4 4 - - - max - - - - - - 30 30 30 tCY tCY tCY tCY tCY tCY ns ns ns Unit
tCY = output system clock (SCKO input) cycle time
VIH SCKO 0.5VDD V IL t BODL t BODL t LODL VOH LRCO 0.5VDD V OL
VOH BCKO 0.5VDD V OL t BOCWH t BOCY VOH DOUT 0.5VDD V OL t DODL t BOCWL
NIPPON PRECISION CIRCUITS INC.--9
SM5950AM
FUNCTIONAL DESCRIPTION
Input Interface Settings (IMOD0, IMOD1, IISI)
Input data format 2s-complement, MSB-first, L/R alternating serial data
IMOD0 L H L H H or L IMOD1 L L H H H or L IISI L L L L H Format 16-bit MSB-first right-justified 20-bit MSB-first right-justified 24-bit MSB-first right-justified MSB-first left-justified (leading 16 bits valid data) IIS (leading 16 bits valid data)
Note: L = Low input level, H = high input level
Input timing The input timing for each input format is shown in figures 4 to 8.
Output System Clock (SCKO)
A clock with frequency 512 times the output sampling frequency (fso) must be input on SCKO. In master mode, the LRCO and BCKO output clocks are derived from the input clock on SCKO. It also functions as the internal computation circuit system clock.
Output Interface Settings (OMOD0, OMOD1, IISO, THROU, SLAVE)
Output data format 2s-complement, MSB-first, L/R alternating serial
OMOD0 L H L H H or L OMOD1 L L H H H or L IISO L L L L H Format 16-bit MSB-first right-justified 20-bit MSB-first right-justified 24-bit MSB-first right-justified MSB-first left-justified (16-bit output) IIS (16-bit output)
Note: L = Low input level, H = high input level
Output mode select
Pin setting THROU L H H H or L Slave Through LRCO and BCKO are supplied externally. Function as inputs LRCO, BCKO, and DOUT are connected directly to LRCI, BCKI, and DI inputs. Function as outputs Note: DMUTE is valid. SLAVE L Mode Master Function Description LRCO and BCKO are derived form SCKO. LRCO, BCKO Function as outputs
Output timing The timing for each output format is shown in figures 9 to 13. In slave mode, the input timing of LRCO and BCKO for each output format is shown in figures 9 to 13. In through mode, the LRCI, BCKI, and DI inputs are fed through to the outputs regardless of the output data format settings.
NIPPON PRECISION CIRCUITS INC.--10
SM5950AM
System Reset (RSTN)
The SM5950AM must be reset if any of the following conditions occur during normal operation. A reset pulse is a LOW-level pulse applied to RSTN, although the reset operation actually occurs on the rising edge of the LOW-level pulse.
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When the power supply is applied
A reset (RSTN = LOW to HIGH) is required when the power supply voltage is applied and after the LRCI, BCKI, SCKO (and LRCO, BCKO if in slave mode) clocks have stabilized.
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When the LRCI and BCKI clocks are interrupted
This occurs when the sampling frequency is switched, when clocks stop due to a condition in a previous stage, when the LRCI, BCKI clocks are dynamically switched, or when otherwise the clocks are not continuous. A reset (RSTN = LOW to HIGH) is required after the LRCI, BCKI clocks have stabilized.
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When the SCKO (and LRCO, BCKO if in slave mode) clocks are interrupted
This occurs when the sampling frequency is switched, when clocks stop due to a condition in a previous stage, when the SCKO, LRCO, BCKO clocks are dynamically switched, or when otherwise the clocks are not continuous. A reset (RSTN = LOW to HIGH) is required after the SCKO, LRCO, BCKO clocks have stabilized. A reset pulse is required under these conditions because the conversion ratio calculated based on such non-continuous clocks will result in an incorrect conversion ratio, and hence the output data will have incorrect values. Output state during reset interval DOUT is tied LOW during the reset interval (refer to section "Direct Mute" for operation after the reset is released). In master mode, the LRCO and BCKO clocks are also tied LOW.
Direct Mute (DMUTE)
Direct mute ON/OFF
DMUTE L H Function Audio data output starts from the next output word. 0 data is output from the next output word.
Other mute operations Direct mute also occurs at system reset.
RSTN L H Function 0 data is output from the next output word. Computed data output starts after 8 output word cycles.
NIPPON PRECISION CIRCUITS INC.--11
SM5950AM
Sample Rate Conversion
The input/output sample rate conversion ratio is variable over a range 0.45 to 2.205 times frequency. The input sample rate (fsi) range is 20kHz to 100kHz, while the output sample rate (fso) range is 30kHz to 50kHz. Note that the sample rate conversion ratio lower limit means that conversion from fsi = 96kHz to fso = 32kHz is not possible. Anti-aliasing filter selection The following 6 filters are provided to function as anti-aliasing filters during sample rate conversion, where the optimum anti-aliasing filter is automatically selected in response to the automatic measurement of the sample conversion ratio between the input sampling frequency (on LRCI) and the output sampling frequency (calculated using SCKO as reference).
Filter mode 1 2 3 4 5 6 fs conversion ratio (fso/fsi) 1.0 to 2.205 times 0.91875 times 0.72562 times 0.66667 times 0.50000 times 0.459375 times Selects range 0.969697 times 0.864865 to 0.969697 times 0.711111 to 0.864865 times 0.627451 to 0.711111 times 0.492308 to 0.627451 times 0.492308 times Conversion frequency (example) Up conversion 48.0 44.1 44.1 32.0 48.0 32.0 96.0 48.0 96.0 44.1
If the selected anti-aliasing filter fs conversion ratio and the actual sample rate conversion ratio do not match, the following phenomena occur.
Conversion condition Response generated
Actual sample rate conversion ratio is lower than the High-frequency aliasing noise occurs in the audio band. selected filter conversion ratio. Actual sample rate conversion ratio is higher than the Primarily cuts high-frequency components in the audio selected filter conversion ratio. band.
If the fs conversion ratio is not fixed, the conversion will slowly follow the change in ratio, but in the process the possibility exists that noise may occur in the audio data output.
NIPPON PRECISION CIRCUITS INC.--12
SM5950AM Conversion performance
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Internal data word length: 20 bits Gain deviation from deemphasis filter ideal characteristic: 0.03dB Anti-aliasing filter characteristic * Passband ripple: 0.0001dB * Stopband attenuation: > 98dB Conversion insertion quantization noise level * Internal computation noise: - 96dB * Output round-off noise: 16-bit output: - 98dB 20-bit output: - 122dB 24-bit output: - 146dB
Overall theoretical output S/N ratio
Output signal word length 16 bits 20 bits 24 bits S/N ratio 16-bit input - 92.5dB - 93.9dB - 93.9dB 20-bit input - 94.0dB - 96.2dB - 96.2dB 24-bit input - 94.0dB - 96.2dB - 96.2dB
Anti-aliasing filter characteristics
48 to 24kHz 48 to 22.05kHz 48 to 32kHz 44.1 to 32kHz 48 to 44.1kHz up conversion
0 -20
Attenuation [dB]
-40 -60 -80 -100 -120 0 0.1 0.2 0.3 Frequency [x fsi] 0.4 0.5 0.6
Figure 1. Anti-aliasing filter characteristics
NIPPON PRECISION CIRCUITS INC.--13
SM5950AM
Deemphasis (DEEM)
Basic deemphasis filters are realized using analog circuit configurations. Here, an IIR digital deemphasis filter configuration faithfully reproduces the gain and phase characteristics of an analog deemphasis filter. The filter coefficients are set by pins FS0 and FS1 for 3 input sampling frequencies (fsi) of 44.1kHz, 48.0kHz, and 32.0kHz. Deemphasis ON/OFF
DEEM L H Deemphasis OFF ON
Deemphasis filter coefficient selection The deemphasis filter is selected by pins FS0 and FS1.
FS0 L H L H FS1 L L H H fsi 44.1kHz 44.1kHz 48.0kHz 32.0kHz
Deemphasis filter characteristics
0.0 -2.0 Attenuation [dB] -4.0 -6.0 -8.0 -10.0 -12.0 10
44.1kHz 48kHz 32kHz
100
1000 Frequency [Hz]
10000
100000
Figure 2. Deemphasis filter frequency characteristics
0 Phase Characteristics [degree] -10 -20 -30 -40 -50 -60 -70 -80 -90 10 100 1000 Frequency [Hz] 10000 100000
32kHz 44.1kHz 48kHz
Figure 3. Deemphasis filter phase characteristics
NIPPON PRECISION CIRCUITS INC.--14
SM5950AM
Group Delay Time
If tINPUT and tOUTPUT are defined as: tINPUT : Serial input data (fsi rate) read end timing (LRCI clock rising edge) tOUTPUT : Serial output data (fso rate) output start timing (LRCO clock rising edge) the group delay is given by: tOUTPUT - tINPUT = (48.41 8.41)/fsi
1/fs
Serial data input t INPUT
1/fso
(48.41 8.41)/fsi
Serial data output
Data waveform image
t OUTPUT
t OUTPUT - t INPUT t INPUT
t OUTPUT
Response Time
The conversion rate detector stage requires a certain amount of time to calculate the sample rate conversion ratio with accuracy. The minimum response time, after the SM5950AM input sampling frequency (fsi: LRCI input) and output sampling frequency (fso: derived from SCKO) have stabilized sufficiently, is the time required to determine the sample rate conversion ratio to 16-bit accuracy after reset is cleared, and is given by: Response time = 16384/fso (371ms at fso = 44.1kHz)
NIPPON PRECISION CIRCUITS INC.--15
SM5950AM
TIMING DIAGRAMS
Input Timing (LRCI, BCKI, DI)
LRCI (fsi) BCKI (64fsi) DI
Lch
Rch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 4. 16-bit MSB-first right-justified (IMOD0 = L, IMOD1 = L, IISI = L), BCKI = 32fsi to 64fsi
LRCI (fsi) BCKI (64fsi) DI
Lch
Rch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 5. 20-bit MSB-first right-justified (IMOD0 = H, IMOD1 = L, IISI = L), BCKI = 40fsi to 64fsi
LRCI (fsi) BCKI (64fsi) DI
Lch
Rch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Figure 6. 24-bit MSB-first right-justified (IMOD0 = L, IMOD1 = H, IISI = L), BCKI = 48fsi to 64fsi
LRCI (fsi) BCKI (64fsi) DI
Lch
Rch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 7. MSB-first left-justified, leading 16 data bits only are valid (IMOD0 = H, IMOD1 = H, IISI = L), BCKI = 32fsi to 64fsi
LRCI (fsi) BCKI (64fsi) DI
Lch
Rch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 8. IIS, leading 16 data bits only are valid (IMOD0 = H, IMOD1 = H, IISI = H), BCKI = 64fsi only
NIPPON PRECISION CIRCUITS INC.--16
SM5950AM
Output Timing (LRCO, BCKO, DOUT)
LRCO (fso) BCKO (64fso) DOUT
Lch
Rch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 9. 16-bit MSB-first right-justified (OMOD0 = L, OMOD1 = L, IISO = L), BCKO = 64fso only
LRCO (fso) BCKO (64fso) DOUT
Lch
Rch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 10. 20-bit MSB-first right-justified (OMOD0 = H, OMOD1 = L, IISO = L), BCKO = 64fso only
LRCO (fso) BCKO (64fso) DOUT
Lch
Rch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Figure 11. 24-bit MSB-first right-justified (OMOD0 = L, OMOD1 = H, IISO = L), BCKO = 64fso only
LRCO (fso) BCKO (64fso) DOUT
Lch
Rch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 12. MSB-first left-justified, 16-bit output (OMOD0 = H, OMOD1 = H, IISO = L), BCKO = 64fso only
LRCO (fso) BCKO (64fso) DOUT
Lch
Rch
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 13. IIS, 16-bit output (OMOD0 = H, OMOD1 = H, IISO = H), BCKO = 64fso only
NIPPON PRECISION CIRCUITS INC.--17
SM5950AM
TYPICAL APPLICATION CIRCUITS
Input Interface Connection Example
Connection with a digital audio interface receiver (DIR:CS8414) example
FSYNC SCK SDATA Co/F0 5V SEL CS12/FCK M3 M2 M1 C U CBL M0
LRCI BCKI DI DEEM IMOD0 IMOD1 IISI
DIR CS8414
SM5950AM
TMOD0 TMOD1 FS0 FS1
MCU
Output Interface Connection Example
Connection to a digital audio interface transceiver (DIT:CS8402A)
External Clock
24.576MHz (512fso) 6.144MHz (128fso)
SCKO LRCO BCKO DOUT FSYNC
MCK
Level Shifter (3.3V to 5V)
SCK SDATA
OMOD0
SM5950AM
5V M2 M1 M0
OMOD1 IISO THROU SLAVE TMOD0 TMOD1
DIT CS8402A
NIPPON PRECISION CIRCUITS INC.--18
SM5950AM
Connection to MOST Interface Transceiver (OS8104)
24.576MHz (512fso)
SCKO LRCO BCKO DOUT 5V OMOD0 /RD /WR PAR_CP PAR_SRC ASYNC PAD0 PAD1 FSY SCK-SRC_FL SR0-D3
RMCK
SM5950AM
OMOD1 IISO THROU SLAVE TMOD0 TMOD1
MOST OS8104
NIPPON PRECISION CIRCUITS INC.--19
SM5950AM
Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter "Products") are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customer are requested to obtain prior written agreement for such use from NIPPON PRECISION CIRCUITS INC. (hereinafter "NPC"). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this documents are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome, Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: sales@npc.co.jp
NC0101CE 2002.08
NIPPON PRECISION CIRCUITS INC.--20

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